1. Field
Example embodiments are related to a semiconductor device including a trench-type device isolation structure and method of forming the same.
2. Description of Related Art
A device isolation structure used in semiconductor devices electrically isolate unit devices (e.g., field effect transistor (FET), well, memory cells, and/or etc.) located adjacent to each other. Because semiconductor devices are becoming more highly integrated, device isolating technology providing quality insulation within a smaller area is being developed.
A widely used device isolation structure is a trench-type device isolation structure. A trench-type device isolation structure may be realized by forming a trench in a predetermined depth on a semiconductor substrate and then filling the trench with insulation material. A well-known method of forming a trench-type device isolation structure is explained below with reference to FIGS. 1-4.
FIG. 1 to FIG. 4 illustrate cross-sectional views used to describe a method of forming a conventional semiconductor device. In the figures, reference number “30” refers to a first region where density of patterns is high, and reference number “35” refers to a second region where density of patterns is low.
Referring to FIG. 1, a buffer oxide and a hard mask layer (not shown) may be formed sequentially on a semiconductor substrate 1. The hard mask layer, buffer oxide, and the semiconductor substrate 1 are successively etched to form a first and a second trench 4a and 4b. The first trench 4a is formed in the first region 30 to define a first active region, and the second trench 4b is formed in the second region 35 to define a second active region. The width of the second trench 4b is wider than the width of the first trench 4a. Sequentially stacked first buffer oxide pattern 2a and first hard mask pattern 3a are formed on the first active region. Sequentially stacked second buffer oxide pattern 2b and second hard mask pattern 3b are formed on the second active region.
A filling oxide layer (not shown) is formed over the entire surface of the semiconductor substrate 1 to fill the first and second trenches 4a and 4b. The filling oxide layer is planarized until the first and second hard mask patterns 3a and 3b are exposed. Then, first and second filling oxide patterns 5a and 5b are formed to fill the first and second trenches 4a and 4b, respectively.
The method of forming the filling oxide layer with a high-density plasma oxide is widely known. A high-density plasma oxide is formed by repeatedly depositing and etching the oxide layer using a high density plasma. The method of planarizing the filling oxide layer using a chemical mechanical polishing process (hereinafter CMP process) is also widely known. The chemical mechanical polishing process may use a slurry in a solution state including a polishing agent and a pH control agent. The CMP process provides the slurry between a polishing pad and the semiconductor substrate 1 having the filling oxide layer and polishes by contacting the semiconductor substrate 1 and the polishing pad. When the filling oxide layer is polished by the CMP process, a dishing effect may occur in the second filling oxide layer which fills the second trench 4b having a large width. The center of the second filling oxide pattern 5b may be formed lower than the fringe area by the dishing effect.
Referring to FIG. 2, the first and second active regions are exposed by removing the first and second hard mask patterns 3a and 3b and first and second buffer oxide patterns 2a and 2b. The first and second buffer oxide patterns 2a and 2b may be removed by wet etching in order to prevent plasma damage of exposed surfaces of the first and second active regions. At this time, the first and second filling oxide patterns 5a and 5b, which are made of oxide, are also etched. An area along the edge of the top surface of the densely patterned first filling oxide pattern 5a near the first active region may be etched further to form a dent 6.
Referring to FIG. 3, after the first and second active regions are exposed, various processes may be performed. For example, an ion injection process to form a well, an ion injection process to adjust threshold voltage of an electric field effect transistor, and a cleaning process before forming a gate oxide layer may be performed. Before performing the ion injection processes, an ion injection buffer oxide layer may be formed to minimize damage of the exposed active region. The ion injection buffer oxide layer may be removed by certain processes including, for example, a cleaning process, after performing the ion injection processes. The cleaning process before forming the gate oxide layer may remove the natural oxide layer formed in an exposed active region. The first and second filling oxide patterns 5a and 5b may be further etched by various forms of cleaning processes before forming the gate oxide layer. As a result, top surfaces of the first and second filling oxide patterns 5a′ and 5b′ further etched by cleaning processes are formed lower than the surfaces of the active regions. Therefore, the planarization of the semiconductor substrate may be defective.
Referring to FIG. 4, a gate oxide layer 7 is formed in the active regions and a gate conductive layer (not shown) is formed in the semiconductor substrate 1. The gate conductive layer is patterned to form a gate electrode 8 over the first active region. The gate electrode 8 covers the sidewall along the edge of the first active region. Therefore, the hump effect may occur at a transistor having the gate electrode 8 and the characteristics of leakage current within the transistor may be deteriorated.
Impurity ions are injected using the gate electrode 8 as a mask to form source and drain regions (not shown) in the first active region on both sides of the gate electrode 8. A metal silicide may be formed on the surface of the source and drain regions.
Various cleaning processes may be performed after the gate electrode 8 is formed. For example, after the source and drain regions are formed, a cleaning process to remove the surface damage of the first active region on both sides of the gate electrode 8 and/or a cleaning process performed after forming the metal silicide may be performed. Because the cleaning processes are performed after forming the gate electrode 8, the first filling oxide pattern 5a″ and the second filling oxide pattern 5b″ exposed between the gate electrode 8 may be further etched. Top surfaces of the first and second filling oxide patterns 5a″ and 5b″ are further etched by the cleaning processes after the gate electrode 8 is formed. The top surfaces first and second filling oxide patterns 5a″ and 5b″ may be formed lower than the top surfaces of the active regions. An indented region 9 may be formed in the first filling oxide pattern 5a″ between the gate electrodes 8.
According to the above conventional method of forming a semiconductor device, a high density plasma oxide layer is used as the filling oxide layer. Because semiconductor devices are becoming more highly integrated, the gap fill characteristics are reaching a limit due to the high density plasma oxide layer. As a result, a void may occur in the first filling oxide pattern 5a and may decrease reliability of the semiconductor device. For these reasons, new material having better gap fill characteristics are being researched.
The first and second filling oxide patterns 5a and 5b are etched by cleaning processes before forming the gate oxide layer 7. This may cause the dent 6 to be formed or cause the top surfaces of the first and second filling oxide patterns 5a′ and 5b′ to be formed lower than the top surfaces of the active regions. Therefore, the hump effect may occur in the electric field effect transistor.
The first and second filling oxide patterns 5a′ and 5b′ may be further etched by cleaning processes after forming the gate electrode 8 to form an indented region 9 between the gate electrodes 8. Subsequently, formed interlayer oxide layer may not fill the indented region 9 sufficiently because the indented region 9 has a higher aspect ratio. Therefore, a void may occur in the indented region 9 and may decrease reliability of the semiconductor device. Further, if the indented region 9 is filled with a metal layer, a bridge may occur among the unit devices and may cause a defect in the semiconductor device.